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[AK2364] AK2364 two-way radio filterless fm detector lsi 1. features the AK2364 includes 2nd-mixer, agc+bpf, pll fm detector, noise squelch, and rssi circuit. this device can eliminate d to g type ceramic fi lters, quadrature discriminator, and other external components. ? low operating voltage: vdd = 2.6 to 5.5 v ? wide operating temperature: ta = -40 to 85 c ? hi sensitivity: -104dbm at 12db sinad ? built-in 2nd mixer ? local frequency: 45.9mhz, 50.4mhz, 57.6mhz (triple of 15.3, 16.8 and 19.2mhz) ? built-in programmable agc+bpf circuits corresponding to d to g type ceramic filters ? built-in pll fm detector ? rssi function ? built-in noise squelch circuits ? low consumption current: 7ma ? compact plastic packaging, 28-pin qfnj 4.0 x 4.0 x 0.75mm, 0.4mm pitch ms1431-e-01 2012/10 - 1 -
[AK2364] ms1431-e-01 2012/10 - 2 - 2. contents 1. features ............................................................................................................................... 1 2. contents .............................................................................................................................. 2 3. block diagram ..................................................................................................................... 3 4. circuit configuration ............................................................................................................ 4 5. pin/function ......................................................................................................................... 5 6. absolute maximum ratings ................................................................................................. 7 7. recommended operating conditions .................................................................................. 7 8. digital dc characteristics .................................................................................................... 7 9. digital ac timing ................................................................................................................. 8 10. system reset .................................................................................................................. 10 11. power consumption ......................................................................................................... 11 12. analog characteristics ..................................................................................................... 12 13. serial interface configuration .......................................................................................... 16 14. calibration procedure ...................................................................................................... 19 15. recommended external application circuits ................................................................... 21 16. packaging ........................................................................................................................ 25 17. important notice .............................................................................................................. 26
[AK2364] ms1431-e-01 2012/10 - 3 - 3. block diagram mixip if_input bias agndin agndout nrecto nampi nampo deto lo_input discri lpf agccnt control logic viref mix bpf0 bpf1 bpf2 agc1 limiter loin csn sclk sdata avdd avss audioout discout pdout nc nc nc nc agc0 rssiout rssi dvdd dvss noise rectifier noise amp comparato r rstn locap vrefa ldo vss2
[AK2364] ms1431-e-01 2012/10 - 4 - 4. circuit configuration block description mix 2nd-mixer to convert the input signal down to 450hz. agc+bpf the circuit composed of agc and bpf, where the desired signal is amplified and spurious components included in the signal from the 2nd-mixer are eliminated. divider the circuit to divide the signal from loin pin and supply bpf with clk. limter the circuit to amplify the signal filtered at the agc+bpf stage and generate rectangular wave. discri the demodulator circuit with pll fm detector, where the audio signal is recovered. lpf the low-pass filter to eliminate the noise generated at the discri stage. noise amp the amplifier to compose the band-pass filter for noise squelch. noise rectifier the rectification circuit to detect the noise level. comparator the circuit to compare the noise level with reference voltage level. rssi the circuit to indicate the received signal strength indicator(rssi) by generate a dc voltage corresponding to the input level from limiter. viref the circuit to generate internal reference voltage. ldo the circuit to supply 2.7v power for some circuits. control logic the control register controls the status of internal condition by serial data that consists of 1 instruction bit, 6 address bits and 8 data bits. note: when you use AK2364 in avdd=2.6 to 3.6v operation, vrefa pin is connected to avdd pin for power supplying.
[AK2364] ms1431-e-01 2012/10 - 5 - 5. pin/function package signal pin no name type conditions at power down function 1 mixip ai z if positive signal input pin 2 avss pwr - analog ground pin 3 vrefa ai h output pin to connect capacitor for ldo 4 avdd pwr - analog vdd power supply pin 5 nc aio z nc pin 6 nc aio z nc pin 7 nc aio z nc pin 8 nc aio z nc pin 9 rssiout ao z output pin to connect capacitor for received signal strength indicator(rssi) 10 pdout ao z pin1 for discriminator low-pass filter 11 discout ao z pin2 for discriminator low-pass filter 12 audioout ao z demodulated audio signal output pin 13 nampi ai z input pin for noise squelch amplifier 14 nampo ao z output pin for noise squelch amplifier 15 nrecto ai z output pin for the rectification circuit 16 bias ao z output pin to connect bias re sistor for reference voltage 17 agndout ao z analog ground output pin. connect the capacitor to stabilize the analog ground level. 18 agndin ai z analog ground input pin. connect the capacitor to stabilize the analog ground level. 19 vss2 pwr - vss power supply pin. normally supply 0v to this pin. 20 rstn di z hardware reset pin 21 csn di z chip select input pin for serial data 22 sclk di z clock input pin for serial data 23 sdata db - input and output pin for serial data 24 deto do z signal detect output pin 25 dvdd pwr - digital vdd power supply pin. 26 dvss pwr - digital ground pin 27 locap ai z local signal input pin 28 loin ai z local signal input pin note: a : analog, d : digital, pwr : power, i : input, o : output, b : bidirectional , z: high-z, l : low when you use AK2364 in avdd=2.6 to 3.6v operation, vrefa pin is connected to avdd pin for power supplying. please set ldo (low drop out) power off setting. when vrefa pin is supplied by external power supply, absolute maximum ratings and recommended operating conditions are based on avdd level.
[AK2364] ms1431-e-01 2012/10 - 6 - ? pin assignment vre f a avss scl k sdata nc a gndout 32 26 27 6 deto r ssiout nc 5 avdd 4 rstn 17 mixip 1 p dout 8 d iscout 9 csn 18 a udioout 10 bias 20 nampo 12 nampi 11 16 15 dvss 22 dvdd 23 locap 24 nc 7 nrecto 19 n c loin 25 13 14 21 28 vss2 a gndin
[AK2364] ms1431-e-01 2012/10 - 7 - 6. absolute maximum ratings parameter symbol min. max. units avdd -0.3 6.5 v power supply voltage dvdd -0.3 6.5 v ground level vss 0 0 v v in analog -0.3 avdd+0.3 v input voltage v in digital -0.3 dvdd+0.3 v input current (except power supply pin) i in -10 +10 ma storage temperature t stg -55 130 c note : all voltages are relative to the vss pin. caution : exceeding these maximum ratings can result in damage to the device. normal operation cannot be guaranteed under this extreme. 7. recommended operating conditions parameter symbol condition min. typ. max. units operating temperature ta -40 85 c avdd 2.6 3.0 5.5 v power supply voltage dvdd dvdd avdd 2.6 3.0 5.5 v ldo in use 1.35 v analog reference voltage agnd ldo not in use 1/2vdd v output load resistance r l audioout, discount, nampo 30 k output load capacitance c l a udioout, discount, nampo 15 pf note : all voltages are relative to the vss pin. 8. digital dc characteristics parameter symbol condition min. typ. max. units high level input voltage v ih rstn, sclk, sdata csn 0.8dvdd v low level input voltage v il rstn, sclk, sdata csn 0.2dvdd v high level input current i ih vih=dvdd rstn, sclk, sdata csn 10 ua low level input current i il vil=0v rstn, sclk, sdata csn -10 ua high level output voltage v oh ioh=+0.2ma sdata dvdd-0.4 dvdd v low level output voltage v ol iol=-0.4ma sdata, deto 0.0 0.4 v
[AK2364] ms1431-e-01 2012/10 - 8 - 9. digital ac timing 1) serial interface timing AK2364 is connected to a cpu by three-wired interface through csn, sclk and sdata pins, which can make reading and writing data for control registers. serial data named sdata is consist of 1-bit read and write instruction(r/w), 6-bit address (a5 to a0) and 8-bit data (d7 to d0) in one frame. write mode a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 d7 d6 hi-z r/w csn sclk sdata (input) sdata (output) read mode a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 d7 d6 hi-z r/w hi-z csn sclk sdata sdata (input) (output) r/w : instruction bit controls to write data to AK2364 or read back from it. when set to low, AK2364 is in write mode. when set to high, AK2364 is in read mode. a5 to a0: register address to be accessed. d7 to d0: write or read date to be accessed. <1> csn(chip select) is normally selected high for disable. when csn is set to low, serial interface becomes active. <2> in write mode, instruction, address and data input from sdata pin are synchronized and latched with the rising edge of 16 iterations of sclk clock. set to low between address a0 and data d7.input data is fixed synchronized with the rising edge of 16th clock. note that if csn become ?h? before 16th clock, setting data becomes invalid. during the period when csn is set to ?l?, consecutive writing is available. <3> in read mode, instruction and address are synchronized and latched with the rising edge of 7 iterations of sclk clock. and the register data are output from sdata pin synchronized with the falling edge of 9 iterations of sclk clock. the data between address a0 and data d7 is unstable. during the period when data is output, input to sdata must be ?hi-z?. set csn to ?h? once reading is completed because consecutive reading is not valid.
[AK2364] ms1431-e-01 2012/10 - 9 - 2) detail timing chart write mode csn sclk sdata (input) t css t wh t wl t dh t ds r/w a5 a4 a3 a0 d7 d6 d0 d1 sdata (output) high-z t cslh t cshh read mode csn sclk sdata (input) t css t sd t dd r/w a5 a4 a1 a0 sdata (output) high-z t cslh t cd high-z d7 d6 d0 d1 rising and falling time parameter symbol condition min. typ. max. unit csn setup time t css 100 ns sdata setup time t ds 100 ns sdata hold time t dh 100 ns sclk high time t wh 500 ns sclk low time t wl 500 ns csn low hold time t cslh 100 ns csn high hold time t cshh 100 ns sdata hi-z setup time t sd 500 ns sclk to sdata output delay time t dd 20pf load 400 ns csn to sdata input delay time t cd 20pf load 200 ns sclk rising time t r 250 ns sclk falling time t f 250 ns note: digital input and output timing is relative to 0.5dvdd of rising signal and falling signal. v il v ih t r t f sclk
[AK2364] ms1431-e-01 2012/10 - 10 - 10. system reset parameter symbol condition min. typ. max. unit remarks hardware reset signal input width t rstn rstn pin 1 us *1) software reset srst register *2) *1) after power-on, be sure to perform a hardware reset operation (register initialization). the system is reset by a low pulse input of 1 s (min.) and enters the normal operation state. at this moment, the digital (di) pins are set as follows: rstn pin to high, sclk pin to low, sdata pin to low, csn pin to low. rstn v ih v il t rstn *2) when data 0x03:10101010 is written to the srst[7:0] register, software reset is performed. this setting initializes the registers and the operation mode is set to mode 0 (power down). after software reset is completed, this register comes to ?0?.
[AK2364] ms1431-e-01 2012/10 - 11 - 11. power consumption parameter symbol condition min. typ. max. units idd0 mode 0 power down 10 a idd1 mode 1 standby, agn din 0.1 0.2 ma idd2 mode 2 standby, lo buffer, viref 0.6 1.4 ma consumption current idd3 mode 3 when no input signal 7.0 10 ma
[AK2364] ms1431-e-01 2012/10 - 12 - 12. analog characteristics for the following conditions unless otherwise specified: loin=50.4mhz,mixip=50.85mhz, f= 1.5khz, fmod=1khz agc+bpf=f4, the exposure back pad of the package is connected to vss, with the external circuit shown in example page 21 to 24. 1) local parameter symbol condition min. typ. max. units notes local frequency f lo loin 45.9 50.4 57.6 mhz input amplitude v lo loin 0.2 1.0 v pp note) note) input from loin pin through dc cut 2) 2nd mixer parameter condition min. typ. max. units notes input impedance note) 50 note) input frequency f lo +0.45 mhz voltage gain 23 db noise figure 13 db note) include external matching circuit 3) discriminator parameter condition min. typ. max. units notes f= 3.0khz,fmod=1khz, limiter in to audioout note) 60 100 140 mvrms band =1 demodulation output level f= 1.5khz,fmod=1khz, limiter in to audioout note) 60 100 140 mvrms band =0 s/n ratio f= 3.0khz,fmod=1khz, limiter in to audioout note) 50 db band =1 note) with de-emphasis bpf(0.3 to 3khz) 4) rx overall characteristics parameter condition min. typ. max. units notes 12db sinad input sensitivity note) -104 dbm iip3 -16 dbm f= 3.0khz,fmod=1khz, agc+bpf=f3 note) 60 100 140 mvrms band =1 demodulation output level f= 1.5khz,fmod=1khz, agc+bpf=f4 note) 60 100 140 mvrms band =0 f= 3.0khz,fmod=1khz, agc+bpf=f3 note) 40 46 db band =1 s/n ratio f= 1.5khz,fmod=1khz, agc+bpf=f4 note) 34 40 db band =0 note)with de-emphasis bpf(0.3 to3khz)
[AK2364] ms1431-e-01 2012/10 - 13 - 5) rssi characteristics parameter condition min. typ. max. units notes mixip --> rssiout mixip=-100dbm input 0.1 0.36 0.62 v rssi output voltage mixip --> rssiout mixip=-30dbm input 1.4 2.0 2.6 v rssi characteristics (vdd=3v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 mixer input level (dbm) rssi output lvel (v) 6) noise squelch characteristics parameter condition min. typ. max. units notes nrecto --> deto detect high 0.5 0.7 v noise detect level nrecto --> deto detect low 0.3 0.4 v nampi --> nrecto input: 31khz, 0.1mvrms 0.1 0.26 0.36 v noise detect characteristic nampi --> nrecto input: 31khz, 0.25mvrms 0.4 0.65 0.8 v noise detect characteristics (vdd=3v, fin=31khz) 0.0 0.4 0.8 1.2 1.6 0.0 0.1 0.2 0.3 0.4 0.5 0.6 filter amplifier input level [mvrms] nrecto output level [v]
7) agc+bpf characteristics [AK2364] ms1431-e-01 2012/10 - 14 - 7.1) f1 (d type) parameter condition min. typ. max. units notes 430khz -50 db 440khz -6 db 460khz -6 db attenuation characteristics (relative to the gain at 450khz) 470khz -50 db gain ripple within 4507khz 3 db 7.2) f2 (e type) parameter condition min. typ. max. units notes 435khz -50 db 442.5khz -6 db 457.5khz -6 db attenuation characteristics (relative to the gain at 450khz) 465khz -50 db gain ripple within 4505khz 3 db 7.3) f3 (f type) parameter condition min. typ. max. units notes 437.5khz -50 db 444khz -6 db 456khz -6 db attenuation characteristics (relative to the gain at 450khz) 462.5khz -50 db gain ripple within 4504khz 3 db 7.4) f4 (g type) parameter condition min. typ. max. units notes 439khz -50 db 445.5khz -6 db 454.5khz -6 db attenuation characteristics (relative to the gain at 450khz) 461khz -50 db gain ripple within 4503khz 3 db
[AK2364] ms1431-e-01 2012/10 - 15 - bpf f1 (bw=10khz) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 425 430 435 440 445 450 455 460 465 470 475 frequency [khz] gain [db] 0 100 200 300 400 500 g.d.t[. s] gain g.d.t bpf f2 (bw=7.5khz) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 425 430 435 440 445 450 455 460 465 470 475 frequency [khz] gain [db] 0 100 200 300 400 500 g.d.t[. s] gain g.d.t bpf f3 (bw=6khz) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 425 430 435 440 445 450 455 460 465 470 475 frequency [khz] gain [db] 0 100 200 300 400 500 g.d.t[. s] gain g.d.t bpf f4 (bw=4.5khz) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 425 430 435 440 445 450 455 460 465 470 475 frequency [khz] gain[db] 0 100 200 300 400 500 g.d.t[. s] gain g.d.t
[AK2364] ms1431-e-01 2012/10 - 16 - 13. serial interface configuration 1) register configuration name adrs d7(msb) d6 d5 d4 d3 d2 d1 d0(lsb) w/r ldostat pdldon bpf_bw[1:0] lofreq[1:0] bs[1:0] control register 1 0x01 1 0 0 0 0 1 0 1 w/r reserved agc_time[1:0] agc0_ step band cal control register 2 0x02 0 0 0 0 0 1 0 0 w/r srst[7:0] software -reset 0x03 ? ? ? ? ? ? ? ? w note: do not access the data except specified address above.
[AK2364] ms1431-e-01 2012/10 - 17 - 2) description of registers address 0x01 (control register 1) name d7(msb) d6 d5 d4 d3 d2 d1 d0(lsb) control register 1 ldostat pdldon bpf_bw[1:0] lofreq[1:0] bs[1:0] initial value 1 0 0 0 0 1 0 1 ldo setting operation data function 0 1 notes ldo stat output status in ldo power down avss shorted avdd shorted pdldon ldo power control off on bpf band width setting bpf_bw [1] bpf_bw [0] name 6db attenuation 0 1 f1 10khz 0 0 f2 7.5khz 1 0 f3 6khz 1 1 f4 4.5khz local frequency setting lofreq [1] lofreq [0] local frequency 0 0 45.9mhz 0 1 50.4mhz 1 0 57.6mhz note: do no set the combination of the code which is not defined in the table given above. operation mode setting bs[1] bs[0] mode name agndin viref system circuits except agndin, lobuf,viref 0 0 mode0(power-down) off off off 0 1 mode1(standby) on off off 1 0 mode2 on on off 1 1 mode3 on on on
[AK2364] ms1431-e-01 2012/10 - 18 - address 0x02 (control register 2) name d7(msb) d6 d5 d4 d3 d2 d1 d0(lsb) control register 2 reserved agc_time[1:0] agc0_ step band cal initial value 0 0 0 0 0 1 0 0 agc_time[1:0] : agc response time setting this register set response time for agc0 gain and agc1 gain to change by 1step. agc response time [ms] agc0_step=0 setting agc0_step=1 setting agc_time [1] agc_time [0] state a state b state c state a state b state c 0 0 0.56 8.50 8.50 0.38 4.35 4.35 0 1 0.92 8.79 8.79 0.56 4.50 4.50 1 0 1.64 9.37 9.37 0.93 4.79 4.79 1 1 3.08 10.52 10.52 1.66 5.38 5.38 note: values above indicate response time duri ng agc gain changes from maximum to minimum or from minimum to maximum. note: agc response time differs according to the following states. state a: agc0 output level is beyond the upper limit. state b: agc0 output level is within the upper limit and agc1 output level is beyond the upper limit. state c: agc1 output level is under the lower limit. operation data function 0 1 notes agc0_ step agc0 gain switching range setting 1db 2db band demodulated signal level setting (note1) narrow wide cal discriminator circuit calibration start trigger (note2) invalid start note1: when {band} register is set to ?0?, demodulated signal level at audioout pin, when input signal is f= 1.5khz dev, is 100mvrms typ. when {band} register is set to ?1?, demodulated signal level at audioout pin, when input signal is f= 3.0khz dev, is 100mvrms typ. note2: calibration is performed synchronized with the rising edge of {cal}. after calibration is completed, this register is set to ?0? automatically. it takes 1.3ms before calibration is completed. refer to ?calibration procedure? for further information. address 0x03 (software reset) name d7(msb) d6 d5 d4 d3 d2 d1 d0(lsb) software-reset srst[7:0] initial value ? ? ? ? ? ? ? ? when data 0x03:10101010 is written to the srst[7:0] register, software reset is performed. refer to system reset for further information.
[AK2364] ms1431-e-01 2012/10 - 19 - 14. calibration procedure 1) avdd=2.6 to 3.6v operation when you use AK2364 in avdd=2.6 to 3.6v operation, vrefa pin is connected to avdd pin for power supplying. please set ldo (low drop out) power off setting. refer to 4-1) in page 22. AK2364 employs a function to calibrate free-r unning frequency of vco in discriminator and demodulated signal level. before starting rx operation, calibration is required in order to acquire proper vco operation range and demodulated signal level. following procedure is required before calibration in ldo power off setting. <1> start up the external tcxo and continuously supply lo signal to AK2364. <2> set ?11? to 0x01 {bs[1:0]} and start up all circuits. after this operation, the circuits necessary for calibration (lobuf, viref and discriminator) will be powered on and calibration can be possible in 500us. <3> calibration is begun by setting "1" to addres s 0x02 {cal}. when the calibration is executed once, the calibration operation cannot be stopped excluding master reset. even if "0" is written in {cal}, the calibration is completely executed. <4> calibration data is maintained excluding the time when the master reset is executed or dvdd power supply is down. <5> it takes 1.5ms for discriminator to become steady after the calibration is completed. power-up sequence recommendation unstable {bs[1:0]} loin external unstable stable lobuf viref discriminator ?11? ?01? (500 s) (1.3ms) unstable internal discriminator {cal} reset itself automatically after calibration is completed (1.5ms)
[AK2364] ms1431-e-01 2012/10 - 20 - 2) avdd=3.6 to 5.5v operation when you use AK2364 in avdd=3.6 to 5.5v operation, please set ldo power on setting. refer to 4-2) in page 23. following procedure is required before calibration in ldo power on setting. <1> start up the external tcxo and continuously supply lo signal to AK2364. <2> set ?10? to 0x01 {bs[1:0]} and start up viref circuits. this makes ldo set power up standby. <3> set ?0? to 0x01 {ldostat} and ldo output shortened vss once. this makes ldo power up time shortly. <4> set ?1? to 0x01 {ldostat} and ?1? to 0x01 {pdldon}, then ldo power is on. it takes 130ms for agndin pin output voltage to become stable. <5> set ?11? to 0x01 {bs[1:0]} and start up all circuits. after this operation, the circuits necessary for calibration (lobuf,viref and discriminator) will be powered on and calibration can be possible in 500us. <6> calibration is begun by setting "1" to addres s 0x02 {cal}. when the calibration is executed once, the calibration operation cannot be stopped excluding master reset. even if "0" is written in {cal}, the calibration is completely executed. <7> calibration data is maintained excluding the time when the master reset is executed or dvdd power supply is down. <8> it takes 1.5ms for discriminator to become stable after the calibration is completed. power-up sequence recommendation unstable {bs[1:0]} loin externa l unstable sta ble lobuf viref discriminator (500 s) unstable internal discriminato r (1.5ms) { cal} (1.3ms) ?10? ?01? { ldostat} ?11? { pdldon} unstable (50 s) (130ms) (100 s) a gndin stable reset itself automaticall y after calibration is completed note: these values refer to the following recommended external application circuits.
[AK2364] ms1431-e-01 2012/10 - 21 - 15. recommended external application circuits 1) power supply stabilizing capacitors connect capacitors between vdd and vss pins to e liminate ripple and noise included in power supply. for maximum effect, the capacitors should be placed at a shortest distance between the pins. lsi c2 dvdd dvss c1 c2=10 f (electrolytic cap) c1=0.1 f (ceramic cap) 25 26 c2 avdd avss c1 4 2 2) agnd stabilizing capacitors it is recommended that capacitors with 1 f or lager be connected between vss and the agnd and agndin pins to stabilize the agnd signal. the capacitors must be placed as close to the pins as possible. lsi c1 a gndin c1=1 f (electrolytic capac itor) 18 c1 17 a gndout avss avss 3) bias lsi r1=47k 1% r1 16 bias avss
[AK2364] ms1431-e-01 2012/10 - 22 - 4-1) vrefa (avdd=2.6 to 3.6v operation) lsi 3 vrefa 4 a vdd 4-2) vrefa (avdd=3.6 to 5.5v operation) lsi c1=220nf c1 3 vrefa avss 5) mix c1=18pf, l1=470nf for 46.35mhz lsi mixip 1 c1 r1=2.4k c2 l1 r1 c2=10nf if_input c1=15pf, l1=470nf for 50.85mhz c1=12pf, l1=390nf for 58.05mhz 6) loin lsi locap loin 2 8 2 7 avss c1 c2 c1=c2=100pf lo_input
[AK2364] ms1431-e-01 2012/10 - 23 - 7) discriminator c1=1000pf r1=220k lsi discout pdout 10 11 r2=1m r1 c1 r2 8) noise amp the following gives a sample configuration of a bpf when input frequency is 31 khz. some parameters can be calculated using following (1) to (3) equations. r3 c1=0.47uf r1=10k _ + lsi r1 noise amp nampi nampo 14 13 c2=c3=220pf c1 r2=5.6k r3=150k avss r2 c2 c3 )//(4 )3( 2 )2( )c//(2 1 )1( 21 3 2 1 3 2 213 0 rr r q r r g rrr f v = = =
[AK2364] ms1431-e-01 2012/10 - 24 - 9) necto rise time of noise detection is proportionate to c1=0.1uf and internal resistance 75k lsi c1=0.1 f c1 15 nrecto avss 10) rssiout lsi c1=1000pf c1 9 rssiout r1 r1=51k avss 11) deto lsi r1=100k 24 deto dvdd r1
[AK2364] ms1431-e-01 2012/10 - 25 - 16. packaging marking 2364 ywwl contents of ywwl y last digit of calendar year. (year 2011->1, 2012->2) ww: manufacturing week number. l: lot identification, given to each product lot which is made in a week. lot id is given in alphabetical order (a, b, c?). mechanical outline package 28pin qfn (4.0 x 4.0 x 0.7mm, 0.4mm pitch) 2.300.10 note the exposure pad(exposed pad of the center of the package back is connected to opening or vss. 0.05 max 0.08 c 2.300.10 0.400.05 c0.3 1 7 15 21 22 28 14 8 4.000.05 c 0.40 ref 0.180.05 0.07 m c a b 4.000.05 b a 0.750.05
[AK2364] ms1431-e-01 2012/10 - 26 - 17. important notice important notice z these products and their s pecifications are subject to change wi thout notice. when you consider any use or ap plication of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and ot her related information contained in this document are provided only to ill ustrate the operation and application examples of the semiconductor products. you are fully responsible for the in corporation of these external circuits, application circuits, software and other related inform ation in the design of your equipments. akm assumes no responsibility for any lo sses incurred by you or third parties arising from the use of these information herein. akm assumes no liabilit y for infringement of any patent, intellectual property, or other rights in the applicati on or use of such inform ation contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency ex change, or strategic materials. z akm products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other haz ard related device or system note2) , and akm assumes no responsibility for such use, exc ept for the use approved with t he express written consent by representative director of akm. as used here: note1) a critical component is one whose failu re to function or perform may reasonably be expected to result, whether directly or indirectly , in the loss of the safe ty or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nucl ear energy, or other fields, in which its failure to function or perfo rm may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buy er or distributor of akm products, who distributes, di sposes of, or otherwise places the product with a third party, to notify such thir d party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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